- 您现在的位置：买卖IC网 > Sheet目录1214 > EVAL-ADM1031EB (ON Semiconductor)BOARD EVAL FOR ADM1031
ADM1031
of a PWM high output if fan speed measurement is enabled
(Bit 2 and Bit 3 of Configuration Register 2 = 1). It then
starts counting on the rising edge of the second tach pulse
and counts for two fan tach periods, until the rising edge of
the fourth tach pulse, or until the counter overranges if the
fan tach period is too long. The measurement cycle repeats
until monitoring is disabled. The fan speed measurement is
stored in the fan speed reading register at address 0 ? 08,
0 ? 09. The fan speed count is given by:
Count + (f 60) R N (eq. 17)
where:
f = 11.25 kHz
R = Fan Speed in RPM
N = Speed Range (either 1, 2, 4, or 8)
The frequency of the oscillator can be adjusted to suit the
expected running speed of the fan by varying N, the speed
range. The oscillator frequency is set by Bit 7 and Bit 6 of
Fan Characteristics Register 1 (0 ? 20) and Fan
Characteristics Register 2 (0 ? 21) as shown in Table 15.
Figure 37 shows how the fan measurements relate to the
PWM_OUT pulse trains.
Table 15. OSCILLATOR FREQUENCIES
FAN_FAULTs
The FAN_FAULT output (Pin 8) is an active-low,
open-drain output used to signal fan failure to the system
processor. Writing a Logic 1 to Bit 4 of Configuration
Register 1 (0 ? 00) enables the FAN_FAULT output pin. The
FAN_FAULT output is enabled by default. The
FAN_FAULT output asserts low only when five consecutive
interrupts are generated by the ADM1031 device due to the
fan running underspeed, or if the fan is completely stalled.
Note that the Fan Tach High Limit must be exceeded by at
least one before a FAN_FAULT can be generated. For
example, if we are only interested in getting a FAN_FAULT
if the fan stalls, then the fan speed value is 0 ? FF for a failed
fan. Therefore, we s hould make the Fan Tach High
Limit = 0 ? FE to allow FAN_FAULT to be asserted after five
consecutive fan tach failures.
Figure 38 shows the relationship between INT,
FAN_FAULT, and the PWM drive channel. The
PWM_OUT channel is driving a fan at some PWM duty
cycle, 50% for example, and the fan’s tach signal (or fan
current for a 2-wire fan) is being monitored at the
TACH/AIN pin. Tach pulses are being generated by the fan,
during the high time of the PWM duty cycle train. The tach
is pulled high during the off time of the PWM train because
the fan is connected high-side to the n-MOS device.
Bit 7
0
0
1
1
Bit 6
0
1
0
1
N
1
2
4
8
Oscillator Frequency (kHz)
11.25
5.625
2.812
1.406
Suppose the fan has twice previously failed its fan speed
measurement. Looking at Figure 38, PWM_OUT is brought
high for two seconds, to restart the fan if it has stalled.
Sometime later a third tach failure occurs. This is evident by
the tach signal being low during the high time of the PWM
pulse, causing the fan speed reading register to reach its
CLOCK
CONFIG 2
REG. BIT 2
FAN
INPUT
START OF FAN
MONITORING MEASUREMENT
CYCLE PERIOD
Figure 37. Fan Speed Measurement
In situations where different output drive circuits are used
for fan drive, it can be desirable to invert the PWM drive
signal. Setting Bit 3 of Configuration Register 1 (0 ? 00) to 1,
inverts the PWM_OUT signal. This makes the PWM_OUT
pin high for 100% duty cycle. Bit 3 of Configuration
Register 1 should generally be set to 1 when using an n-MOS
device to drive the fan.
If using a p-MOS device, Bit 3 of Configuration
Register 1 should be cleared to 0.
maximum count of 255. Since the tach limit has been
exceeded, an interrupt is generated on the INT pin. The fan
fault bit (Bit 1) of Interrupt Status Register 1
(Register 0 ? 02) is also asserted. Once the processor has
acknowledged the INT by reading the status register, the
INT is cleared. PWM_OUT is then brought high for another
two seconds to restart the fan. Subsequent fan failures cause
INT to be reasserted and the PWM_OUT signal is brought
high for two seconds (fan spin-up default) each time to
restart the fan. Once the fifth tach failure occurs, the failure
is deemed to be catastrophic and the FAN_FAULT pin is
asserted low. PWM_OUT is brought high to attempt to
restart the fan. The INT pin continues to generate interrupts
after the assertion of FAN_FAULT since tach measurement
continues even after fan failure. Shoul d the fan recover from
its failure condition, the FAN_FAULT signal is negated, and
the fan returns to its normal operating speed.
Figure 39 shows a typical application circuit for the
ADM1031. Temperature monitoring can be based around a
CPU diode or discrete transistor measuring thermal
hotspots. Either 2- or 3-wire fans can be monitored by the
ADM1031, as shown.
http://onsemi.com
23
发布紧急采购，3分钟左右您将得到回复。
相关PDF资料
EVAL-ADM1062TQEBZ
BOARD EVALUATION FOR ADM1062TQ
EVAL-ADM1075CEBZ
BOARD EVAL FOR ADM1075
EVAL-ADM1087EBZ
BOARD EVALUATION FOR ADM1087
EVAL-ADM1166TQEBZ
BOARD EVAL FOR ADM1166TQ
EVAL-ADM1168LQEBZ
BOARD EVAL FOR ADM1168LQ
EVAL-ADM1170EBZ
BOARD EVALUATION FOR ADM1170
EVAL-ADM1171EBZ
BOARD EVALUATION FOR ADM1171
EVAL-ADM1172EBZ
BOARD EVALUATION FOR ADM1172
相关代理商/技术参数
EVAL-ADM1034EB
制造商:ON Semiconductor 功能描述:EVAL BOARD - Boxed Product (Development Kits)
EVAL-ADM1060EBZ
功能描述:BOARD EVALUATION ADM1060 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源
EVAL-ADM1062-69CSZ
功能描述:EVAL BOARD ADM1062 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081
EVAL-ADM1062LFEB
功能描述:BOARD EVALUATION FOR ADM1062LF RoHS:否 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源
EVAL-ADM1062LFEBZ
制造商:Analog Devices 功能描述:EVALUATION KIT FOR ADM1062 制造商:Analog Devices 功能描述:EVAL KIT FOR ADM1062 - Bulk
EVAL-ADM1062TQEB
制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-ADM1062TQEBZ
功能描述:BOARD EVALUATION FOR ADM1062TQ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081
EVAL-ADM1063LFEB
制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk